Does Ram Latency make any Difference for any projects?

Hardware upgrades, reuse, repairs, and optimizations. Fire hazards and bleeding edges.
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endgame124
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Does Ram Latency make any Difference for any projects?

Post by endgame124 »

After much tweaking and experimentation, I have found the only way to fully expunge WHEA errors from my new machine is top drop ram frequency to 3667. While a new bios may eventually raise this, for now I'm stuck at 3667. I was toying with the idea of picking up a CL 14-14-14 3600 or 3800 32GB kit (+$30 for 3800) and dropping my primary latency settings from 18-20-20. Will any DC projects take advantage of this? I'll take my existing kit 64GB kit and throw it in my new freenas.

Thoughts?
StefanR5R
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Re: Does Ram Latency make any Difference for any projects?

Post by StefanR5R »

Short answer: Maybe…?

Long answer:
  • PrimeGrid LLR based subprojects depend somewhat on RAM performance if they are configured to fit into the processors' last level caches, and highly depend on it if not. What matters more – latency or bandwidth – is not known to me. Perhaps bandwidth, as the task is to feed the vector units. But latency should matter too, as the task is to feed several vector units at once. A long while ago I tried a 4-core laptop with different RAM populations, but I didn't test for bandwidth and latency impacts independently.

    The PrimeGrid LLR based subprojects can be very precisely benchmarked if one and the same workunit is used for benchmarking. The linked test still used random workunits. SoB-LLR was used in the test, and single-threaded even; that is, the workload exceeded the processor caches by far.
  • Rosetta@home depends on RAM performance. Again I don't know what's more important, bandwidth or latency. I also haven't looked into implementing a Rosetta benchmark. A fixed workunit should be used; random workunits will give random results.
  • WCG MIP, while using the same fundamental code as Rosetta, seems to be even more dependent on RAM performance. Again I'm not sure about bandwidth vs. latency, haven't done a benchmark yet, believe that a fixed workunit should be used for benchmarking.

    IIRC, a Xeon E5 v4 with 2 DIMMs per channel gave a little better performance in WCG MIP as a same E5 v4 with 1 DIMM per channel. (2 DPC config: reg-ecc DDR4-2400 c17 single-rank, probably dropped down to 2133 but I can't check right now. 1 DPC config: reg-ecc DDR4-2400 c17 single-rank, at its rated speed of 2400.) The 2 DPC config probably has some sort of interleaving enabled between DIMMs on the same channel.

    There is a variety of projects in which the performance of these Xeons with their different memory configuration is indistinguishable.
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